1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a transistor structure for a semiconductor device and a method of fabricating the same.
2. Description of the Related Art
Generally, most electronic appliances include semiconductor devices. A semiconductor device may include electronic elements, e.g., a transistor, a resistor, and a capacitor, which may be designed to perform partial functions of the electronic appliance and may be integrated on a semiconductor substrate. For example, some electronic appliances, such as a computer or a digital camera, may include semiconductor devices, e.g., memory chips for storing data and processing chips for controlling data, and the memory chips and processing chips may each include electronic elements integrated on a semiconductor substrate.
To help meet customers' demands for better performance and lower prices, semiconductor devices are becoming more and more highly integrated. According to Moore's law or Hwang's law, the integration density of semiconductor devices has doubled at intervals of 18 months or one year, respectively, and it is expected that semiconductor devices will become more highly integrated in the future. This increase in the integration density of the semiconductor devices can be accomplished by shrinking the planar areas of electronic devices of the semiconductor devices. However, the respective electronic devices should satisfy various characteristics required for the normal operations of the semiconductor devices. This technical demand makes it difficult to shrink the planar areas of the electronic devices.
A short channel effect, which may occur, e.g., in MOS transistors, is a typical example of technical restrictions that preclude shrinking areas of semiconductor devices. The short channel effect may occur when a channel length, i.e., a distance between a source electrode and a drain electrode, of a transistor is decreased, and the short channel effect may degrade the characteristics of a transistor. For example, the short channel effect may give rise to, e.g., punch-through, drain induced barrier lowering (DIBL), subthreshold swing, a gain in parasitic capacitance and/or a rise in leakage current between the source and drain electrodes and a substrate. Such problems impose a technical limitation on reducing the channel length of transistors.
For a semiconductor device including a planar MOS transistor, reducing a channel width W of the transistor may be considered as another method for increasing the integration density of the semiconductor device. However, as expressed in following Equation 1, because a drain current Id may be proportional to the channel width W, a reduction in the channel width W may bring about a drop in current driving capability.
                                          I            d                    =                                    W              L                        ⁢                          f              ⁡                              (                                                      V                    G                                    ,                                      V                    T                                    ,                                      V                    DS                                                  )                                                    ,                                  ⁢                              where            ⁢                                                  ⁢            L                    =                      channel            ⁢                                                  ⁢            length                                              (        1        )            
Thus, for a typical planar MOS transistor, attempts at increasing the degree of integration of a device may be difficult to do while maintaining and/or improving characteristics of the transistor.
Attempts for overcoming the technical restrictions of planar MOS transistors have proposed a FIN field effect transistor (FIN-FET) and a multi-channel FET.
FIG. 1A illustrates a perspective view of a conventional FIN-FET, and FIG. 1B illustrates a diagram for explaining problems associated with fabrication of the conventional FIN-FET. Referring to FIG. 1A, the FIN-FET 10 may include a FIN-type active pattern 5, a gate pattern 7 covering a top surface and sidewalls of the active pattern 5 across the active pattern 5, and a gate insulating layer 6 interposed between the gate pattern 7 and the active pattern 5. The FIN-FET 10 may employ the top surface and both sidewalls of the active pattern 5 as a channel region, so a channel width of the transistor can be increased more than that of a planar MOS transistor.
However, referring to FIG. 1B, forming the active pattern 5 may include forming a predetermined preliminary mask pattern 2 and forming a mask pattern 4, using a predetermined recess process, which has a width smaller than the width of the preliminary mask pattern 2. The resultant mask pattern 4 may be used as an etch mask for forming the active pattern 5. In this case, the preliminary mask pattern 2 may be formed to a nonuniform width, as shown in FIG. 1B, and the nonuniform width of the preliminary mask pattern 2 may be transferred to the active pattern 5. Even if a ratio of a variation Δw of the width of the preliminary mask pattern 2 to the entire width w1 of the preliminary mask pattern 2 is small, a ratio of the variation Δw of the width w1 of the preliminary mask pattern 2 to the width w2 of the mask pattern 4 or the width w3 of the active pattern 5 is large. This nonuniform width of the preliminary mask pattern 2 may cause the characteristics of the FIN-FET to be unstable.
FIG. 2A illustrates a cross sectional view of a conventional multi-channel FET, and FIG. 2B illustrates a diagram for explaining problems associated with the conventional multi-channel FET.
To overcome such non-uniformity in the width of the active region of the FIN-FET, the multi-channel FET 20 may be formed to have the structure illustrated in FIGS. 2A and 2B. Forming the multi-channel FET 20 may include forming a mask pattern 24 and forming an active pattern 26. The mask pattern 24 may be formed with a gap region 23 by etching a central portion of a preliminary mask pattern 22. The active pattern may be formed using the mask pattern 24 illustrated in FIG. 2B as an etch mask. Thus, a groove region 27, which may penetrate the active pattern 26, may be formed at a position corresponding the gap region 23, as shown in FIG. 2A. Thereafter, a gate insulating layer 28 may be formed on the surface of the active pattern 26, and a gate pattern 29 may be formed on the gate insulating layer 28 across the groove region 27. Generally, a channel region of transistor is a region where the gate pattern 29 intersects the active pattern 26. Thus, portions of the active patterns 26 bordering the groove region 27 may only be used for the channel region of the multi-channel FET 20.
For this reason, it may be difficult to fabricate transistors with various channel widths using the multi-channel FET 20. That is, because a channel width of the multi-channel FET 20 may be proportional to a number of the active patterns 26 constituting the channel region, the channel width of the multi-channel FET 20 is substantially discrete. In particular, a height of the active pattern 26 may be a process parameter that may affect the characteristics of various transistors. Thus, the height of the active pattern 26 cannot be arbitrarily changed. The fixed height of the active pattern 26 may hinder overcoming the above-described discreteness of the channel width of the multi-channel FET 20.